An LD-MOS transistor is known as a switching transistor for driving the load that requires a high drive current, such as a motor.
FIG. 1 shows the structure of such an n-channel LD-MOS transistor.
In FIG. 3, an n well 9 is formed on a surface of a p-type silicon semiconductor substrate 11, and in the n well 9 is formed a p body region 26 as a p-type diffusion region. On the surface of the p body region 26 is formed an n.sup.+ source region 27. On the surface of the n well 9 is formed an n.sup.+ drain region 28. A gate insulation layer 21 is deposited on the surfaces of the n.sup.+ source region 27, p body region 26, n well 9 and n.sup.+ drain region 28. A conductive gate layer 22 is deposited on the gate insulation layer 21. A source electrode S is connected to the p body region 26 and n.sup.+ source region 27. A gate electrode G is connected to the conductive gate layer 22. A drain electrode D is connected to the n.sup.+ drain region 28.
With such an LD-MOS transistor, a channel Q which determines the turn-on resistance during the switching operation is formed between the boundary of the n.sup.+ source region 27 underlying the gate insulation layer 21 and the boundary of the p body region 26. Thus, with this LD-MOS transistor, the turn-on resistance can be lowered by reducing the channel length, without reducing the distance between the n.sup.+ source region 27 and drain region 28.
With the LD-MOS transistor as shown in FIG. 1, a structure is known where breakdown strength is increased by widening the gap between the n.sup.+ source region 27 and drain region 28.
FIG. 2 shows one example of such an LD-MOS transistor, where like parts shown in FIG. 1 are denoted by the same reference symbols.
With such an LD-MOS transistor, breakdowns strength can be controlled by forming an insulation layer 18 thicker than the gate insulation layer 21 through diffusion of SiO.sub.2 and so on, thereby permitting any distance to be set (over the diffusion) between the n.sup.+ source region 27 and drain region 28.
However, with such an LD-MOS transistor, there is a problem that because the distance between the n.sup.+ source and drain regions 27 and 28 must be widened according to the increasing breakdown strength, the real estate occupied by the device itself is also increased. Furthermore, because the breakdown strength value of such a transistor also depends on the depth of the n well 9, a method is also available for achieving increased breakdown strength by increasing the depth of the n well 9; however, the depth of the n well 9 is limited in terms of manufacturability, so that a desired breakdown strength value cannot be obtained.
Accordingly, it is an object of the present invention to provide an LD-MOS transistor that is easily manufacturable and also permits switching operation with a minimized real estate of the device and increased breakdown strength.